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# 如何在Verilog中解释阻塞与非阻塞分配？

2019-09-24 16:22:05

output logic[7:0] f);

logic[7:0] a, b, c;

always_ff @(posedge clock)

begin

a = b + c;

b = c + a;

c <= a + b;

end

assign f = c;

endmodule

## 3 回答

(

input clock,

input [7:0] in1,

input [7:0] in2,

output logic [7:0] f1, f2, f3, f4, f5

);

// f1 will be a flipflop

always_ff @(posedge clock) begin

f1 = in1 + in2;

end

// f2 will be a flipflop

always_ff @(posedge clock) begin

f2 <= in1 + in2;

end

// f3 will be a flipflop

// c1 will be a flipflop

logic [7:0] c1;

always_ff @(posedge clock) begin

c1 <= in1 + in2;

f3 <= c1 + in1;

end

// f4 will be a flipflop

// c2 is used only within the always block and so is treated

// as a tmp variable and won't be inferred as a flipflop

logic [7:0] c2;

always_ff @(posedge clock) begin

c2 = in1 + in2;

f4 = c2 + in1;

end

// c3 will be a flipflop, as it's used outside the always block

logic [7:0] c3;

always_ff @(posedge clock) begin

c3 = in1 + in2;

end

assign f5 = c3 + in1;

endmodule

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